Timing Analysis in High Speed PCB Design

For digital system design engineers, timing analysis is an important part of high-speed PCB design. Especially with the emergence of the 100M bus, after the signal edge rate reaches picoseconds, the system performance is more dependent on the front-end design, which requires accurate timing analysis and calculation at the beginning of the design. Timing analysis and signal integrity are inseparable, and good signal quality is the key to ensuring timing relationships. Signal quality problems caused by reflection, crosstalk and other phenomena are likely to bring timing shift and disorder, and we must consider the two together when designing.

The starting point of timing analysis is to determine the design scheme according to the signal establishment or hold time relationship. This method runs through the entire design process, including IC design, board design and system design.

Time-of-flight refers to the difference from the moment when the signal is sent to the moment when the signal is stable at the receiving end, and is used to express the delay caused by wiring and load. In the case of low speed, it can be determined by approximate method, but in the design of high-speed pcb, it must be determined by simulation method due to factors such as load and transmission line effect. After the time of flight is determined, the timing calculation can be implemented using a table or manual method to check whether the signal meets the signal sample and hold requirements. Similarly, reverse this process to obtain routing length rules.

The characteristic of the common clock mode is that the clocks of the transceivers are provided by the common clock source. It has two characteristics. One is that the data needs to reach the receiving end within one cycle, and the second is that the clock difference has a great influence on the timing.

Usually when the clock and data are driven by the same type of interface, the timing calculation only needs to consider the phase difference between them. If this is not the case, the phase difference (such as the wiring length) needs to be adjusted according to the flight time. The method in the sense that the data clock routing is of equal length becomes ineffective.

In the design, other factors such as switching noise, inter-symbol interference, and non-ideal loops have an impact on the signal phase. Therefore, on the one hand, we should reasonably add design margins in the timing design, and on the other hand, we need to adopt other design methods to reduce the influence of interference.